2021: Synopsys Design Compiler Tutorial

# Redirect diagnostic reporting into specific files report_area -hierarchy > ../reports/area.rpt report_power > ../reports/power.rpt report_constraint -all_violators > ../reports/constraints_violators.rpt # Generate a detailed path report for the worst critical timing path report_timing -delay_type max -max_paths 10 > ../reports/timing_max.rpt Use code with caution. Phase 5: Exporting the Synthesized Netlist

Weaknesses

set tech_path "/path/to/tech_libs" set lib_path "/path/to/cell_libs" # Target Library (for mapping logic gates) set target_library [list $lib_path/sc_max.db] # Link Library (includes target library + standard cells + IP) set link_library [list * $target_library $tech_path/io_max.db] # Symbol Library (for schematic viewing) set symbol_library [list $tech_path/generic.sdb] Use code with caution. 3. The Synthesis Flow Steps synopsys design compiler tutorial 2021

source constraints.sdc check_timing > reports/check_timing.rpt

Accounts for delays outside the current module. The Synthesis Flow Steps source constraints

set_load 0.05 [get_ports dout*] set_driving_cell -lib_cell BUFFD2 [get_ports din*]

cd work dc_shell -f ../scripts/synthesis.tcl | tee synthesis.log Use code with caution. Graphical User Interface (GUI) Mode Step 1: Reading the RTL Source Code By

[Read RTL] ──> [Link Design] ──> [Apply Constraints] ──> [Compile/Optimize] ──> [Analyze Reports] ──> [Save Outputs] Use code with caution. Step 1: Reading the RTL Source Code

By the end of this guide, you will understand how to: